verilator
Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling. More information: <https://veripool.org/guide/latest/>.
RUN apt-get update && \
apt-get install -y verilator
RUN apt-get update && \
apt-get install -y verilator
RUN pacman -S --noconfirm verilator
RUN apt-get update && \
apt-get install -y verilator
RUN dnf install -y verilator
RUN apt-get update && \
apt-get install -y verilator